The present invention relates to a semiconductor substrate, a method for fabricating the same, and a method for fabricating a semiconductor device.
The recent rapid advancement of miniaturization technology has achieved an exponential increase in the number of semiconductor elements in a semiconductor device, i.e., a higher degree of integration. Accordingly, active regions to be formed with semiconductor elements and isolation regions between the semiconductor elements have been reduced in size significantly. As a result, STI (Shallow Trench Isolation) which buries an oxide insulating film in fine trenches provided in a substrate has been used as a replacement isolation method for LOCOS isolation involving an oxidation process.
A specific method for forming the STI is as follows. First, isolation trenches are formed in a substrate and then an oxide insulating film is buried in each of the isolation trenches by CVD (Chemical Vapor Deposition). Thereafter, the portions of the oxide insulating film formed on active regions are removed by CMP (Chemical Mechanical Polishing), while the surfaces of the portions of the oxide insulating film buried in the isolation trenches are planarized, whereby steps produced on the surfaces of isolation regions and the active regions are removed.
When CMP is performed, an end-point detection film for notifying whether or not planarization of an entire semiconductor wafer or in terms of semiconductor devices (chips) has been accomplished is formed under the oxide insulating film, as shown in, e.g., Japanese Laid-Open Patent Publication No. 9-36073. At present, a nitride film (SiN film) is used normally as the end-point detection film. When the nitride film is used as the end-point detection film, polishing conditions including a load (load under which a wafer is pressed against a polishing pad) and the speed of rotation (the speed of rotation of each of the polishing pad and the wafer) are set such that a polishing speed for the oxide insulating film is double or more a polishing speed for the nitride film. In a CMP process disclosed in, e.g., Japanese Laid-Open Patent Publication No. 9-36073, the ratio of the polishing speed for the oxide insulating film to the polishing speed for the end-point detection film is about 3 to 5.
A typical polishing sequence for CMP is as follows. That is, since the reflectivity of light detected by an end-point detector or the torque of a motor for rotating the platen of a polishing apparatus changes upon the exposure of the nitride film (end-point detection film), the polishing speed for the nitride film is reduced abruptly starting from the time of exposure, while over polishing is performed, whereby an entire semiconductor wafer is further planarized.
Steps produced on the surface of the substrate when CMP for forming the STI is performed (hereinafter referred to as STI-CMP), i.e., variations in planarization process are substantially determined by variations (surface roughness on the nitride film) in the thickness (final thickness) of the nitride film remaining on the surface of the substrate. In the case of forming, e.g., a MOS transistor on a semiconductor substrate, it is necessary to preliminarily remove the nitride film as the end-point detection film. If the final thickness of the foregoing nitride film has variations, steps are produced on the surface of the substrate after the removal of the nitride film to cause size variations in lithography for electrode processing or the like.
In accordance with the conventional STI-CMP, variations in planarization process, i.e., variations in the final thickness of the nitride film can be suppressed to an objective value of about 30 to 50 nm or less at the portion of a semiconductor wafer other than the peripheral edge portion thereof extending radially about 5 mm from the edge surface of the wafer. However, the uniformity of an amount of grinding of the nitride film (the ratio of an error to an objective amount of grinding) cannot be suppressed to 5% or less at the foregoing peripheral edge portion of the wafer (especially in a range of the peripheral edge portion extending radially about 2 to 5 mm from the edge surface of the wafer) and hence the foregoing objective value cannot be achieved. This is a factor which hinders the enlargement of the effective region of the wafer as a determinant of the number of chips obtainable from the semiconductor wafer.
As the miniaturization rules are reduced increasingly from 130 nm to 65 nm, a necessity occurs to suppress variations in the final thickness of an end-point detection film such as a nitride film over the surface of the wafer after STI-CMP to a more stringent objective value of about 20 to 30 nm or less. However, the objective value cannot be achieved by using the conventional CMP technology including the semiconductor wafer, the end-point detection film (such as the nitride film), and the end-point detection method which are used currently in combination. In this case, variations in the final thickness of the end-point detection film eventually lead to steps produced on the isolation region and steps produced on the active region to be formed with a semiconductor element so that a problem such as size variations or an inter-electrode short circuit occurs during the formation of, e.g., the gate electrode of a MOS transistor.